// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_topic_sche_mem_s_cfg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:26:21 Create file
// ******************************************************************************

#ifndef __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_FIELD_H__
#define __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_FIELD_H__

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_0_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_0_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_1_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_1_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_2_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_ENABLE_CTRL_S_2_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_0_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_0_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_1_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_1_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_2_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_ACPU_SLOT_DISABLE_CTRL_S_2_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL0_ACPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL0_ACPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL1_ACPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL1_ACPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL2_ACPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL2_ACPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_0_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_0_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_1_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_1_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_2_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_ENABLE_CTRL_S_2_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_0_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_0_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_1_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_1_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_2_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_CCPU_SLOT_DISABLE_CTRL_S_2_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL0_CCPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL0_CCPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL1_CCPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL1_CCPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL2_CCPU_SLOT_ENABLED_STATUS_S_LEN    8
#define STARS_TOPIC_SCHE_MEM_S_CFG_POOL2_CCPU_SLOT_ENABLED_STATUS_S_OFFSET 0

#endif // __STARS_TOPIC_SCHE_MEM_S_CFG_REG_OFFSET_FIELD_H__
